As is well known, electrically programmable non-volatile memories are constructed as matrices of cells, each comprising a floating gate MOS transistor having respective drain and source regions.
The floating gate is realized over the semiconductor substrate and isolated therefrom by a thin layer of gate oxide. A control gate is coupled capacitively to the floating gate through a dielectric layer. Metal electrodes are provided for contacting the drain, source and control gate in order to apply predetermined voltage values to the memory cell.
By suitably biasing the cell terminals, the amount of charge present in the floating gate can be varied. The operation whereby a charge is built up in the floating gate is called "programming", and consists of biasing the drain terminal and control gate to a predetermined value, higher than the potential of the source terminal.
A non-volatile memory circuit integrated in a semiconductor usually comprises a very large number of memory cells organized into rows (word lines) and columns (bit lines). Cells belonging to the same row share the line which drives their respective control gates. Cells belonging to the same bit line have the drain electrode in common. For programming a given cell, the word line and bit line which identify it must be applied suitable positive voltage values.
A memory cell programming is heavily affected by the voltage Vd applied to the drain terminal, that is, by the voltage present on the bit line to which that cell belongs.
In particular, for non-volatile memory cells of the FLASH type, a low value of said drain voltage Vd results in insufficient and slow programming of the cell, whereas an excessively high value results in the cell being partially erased (the so-called soft-erasing phenomenon). Thus, the optimum range for Vd is rather narrow, typically from 5 V to 6 V approximately.
The above considerations lead one to conclude that the memory circuit should be provided with a sophisticated and precise voltage regulator capable of supplying the appropriate voltage to the bit line during the programming phase.
A first prior approach to meeting this requirement is the so-called correlation by decoding, schematically illustrated in FIG. 1 for a non-volatile memory cell M1.
In particular, the memory cell M1 is connected between a ground voltage reference GND and a program voltage reference Vpp through a series of a voltage regulator 1, connected to the program voltage reference Vpp and to a program load 2, itself connected to the drain terminal D1 of the memory cell M1 via a column decoder 3.
The regulator 1 is effective to limit the current being flowed through the memory cell M1 during the programming phase, by smoothing a secondary program voltage Vpd, specifically the voltage present on a data bus BD between the program load 2 and the column decoder 3.
The program load 2 conventionally comprises a logic inverter IL1 and a transistor M2, specifically a PMOS type.
The drain voltage Vd of the memory cell M1 is therefore the difference between the secondary program voltage Vpd and a voltage .DELTA.V.sub.C equal to the drop across the chain of decode transistors Y0, YN, YM of the decoder 3 and the serial resistances rd of the bit line and rs of the source terminal: EQU Vd=Vpd-.DELTA.V.sub.C (1)
In order to limit this voltage drop .DELTA.V.sub.C, the value of a voltage Vpcy to be applied to the gate terminals of the chain of decode transistors Y0, YN, YM of the decoder 3 should be raised such that they will keep within the so-called "triode" operating range.
For flash memory cells with a dual supply, an active adjustment of the voltage drop .DELTA.V.sub.C can be provided using a feedback differential regulator 4, as shown schematically in FIG. 2.
The differential regulator 4 is connected to the drain terminal D1 of the memory cell M1 through the column decoder 3, and comprises a differential stage 5, itself connected to a redundancy decoder 6, which is connected to the ground voltage reference GND and adapted to mirror a current I.sub.C flowing through the memory cell M1 during the programming phase, via the column decoder 3. This redundancy decoder 6 introduces a voltage drop equal to .DELTA.V.sub.D.
The differential stage 5 has an inverting input terminal 7, a non-inverting input terminal 8, and an output terminal 9. A power supply terminal 10 of the differential stage 5 is further connected to the program voltage reference Vpp.
The inverting input terminal 7 of the differential stage 5 is connected to the ground potential reference GND through a bias transistor M3, spec ifically an NMOS type, which receives a control voltage V.sub.BG independent of temperature on its gate terminal, and through the column decoder 3.
The bias transistor M3 keeps the secondary program voltage Vpd stable outside the memory cell decoding phase, that is outside the current take-up phase of the cells.
The non-inverting input terminal 8 receiving a reference voltage Vref is connected, through a resistive divider R1/R2, to the redundancy decoder 6 and to the bias voltage reference Vpp.
The output terminal 9 is feedback connected to the non-inverting input terminal 8 through a current mirror configuration. In particular, the output terminal 9 is connected to the gate terminal of an output transistor M4, specifically an NMOS type, having its source terminal connected to the drain terminal of the bias transistor M3 and its drain terminal connected to the drain terminal of a first mirror transistor M5, specifically a PMOS type, in diode configuration, that is having its drain terminal connected to the gate terminal, and its source terminal connected to the program voltage reference Vpp.
Furthermore, the gate terminal of the first mirror transistor M5 is connected to the gate terminal of a second mirror transistor M6, specifically a PMOS type, having its source terminal connected to the program voltage reference Vpp and its drain terminal connected to the redundancy decoder 6 and connected to the ground voltage reference GND through an adjust transistor M7, specifically an NMOS type.
The adjust transistor M7 has its source terminal connected to the ground voltage reference GND and its gate terminal connected to the control voltage V.sub.BG independent of temperature. In particular, this adjust transistor M7 eliminates the mirror current contribution K*I.sub.B from the bias transistor M3, which takes up a current I.sub.B.
Finally, it should be noted that the output transistor M4 and bias transistor M3, shown separately for convenience of illustration, are actually parts of an operational amplifier which also includes the differential stage 5.
The architecture of FIG. 2 provides a drain voltage Vd for the memory cell M1 which is substantially independent of the current I.sub.C and of temperature, as by suitable selection of the mirror ratio K for the feedback configuration comprising the transistors M4, M5, M6 and the resistive divider R1/R2.
While achieving its objective, this approach has the following drawbacks:
the final configuration of the feedback differential regulator 4, as shown in FIG. 2, is quite complicated, and the mirror ratio K varies with the number of cells to be programmed; PA1 this feedback differential regulator 4 cannot be used with memory cells having a single supply voltage. PA1 an output voltage having a mean value close to the control voltage V.sub.BG independent of temperature of the bandgap circuit according to the prior art (at room temperature); and PA1 a constant positive drift of the output voltage against temperature.
For such memory cells with a single supply voltage, the high voltage values required for the programming phase must be derived by means of booster circuits, typically charge pumps, from the single supply voltage. When the configuration shown in FIG. 2 is used for the feedback differential regulator 4, the charge pumps for regulating the current to the drain terminal of the memory cell to be programmed should deliver a program voltage Vpp, exceeding the reference voltage Vref by a value at least equal to the threshold voltage of a PMOS transistor, so that the pumps have to be provided oversize.
A feedback differential regulator like that shown in FIG. 2, and intended for a memory cell M1 with a single supply voltage, would therefore be high in area occupation.
To obviate these drawbacks, the state of the art proposes a feedback differential regulator 11 with no adjustment feature, as shown schematically in FIG. 3.
This feedback differential regulator 11 effects no adjustment of the voltage drop .DELTA.V.sub.C across the column decoder 3, either for temperature variations or for the current I.sub.C which is flowing through the memory cells during the programming phase.
In essence, the secondary program voltage Vpd for the drain terminal D1 of the memory cell M1 is derived from a boosted voltage Vpump supplied by a charge pump booster circuit 13. This secondary program voltage Vpd is also set, when no current is being taken up by the memory cell, through the differential stage 5, to be a multiple of a control voltage V.sub.BG independent of the temperature which is generated by a so-called bandgap circuit 12 connected to the inverting input terminal 7 of the differential stage 5.
In this way, the secondary program voltage Vpd will be set under any operational conditions of the circuit, starting from a non-regulated boosted voltage Vpump. Thus, the charge pump booster circuit 13 functions as a current reservoir.
For the purpose, the output terminal 9 of the differential stage 5 is feedback connected to the power terminal 10 through an output transistor M8, specifically a PMOS type. In addition, the power terminal 10 receives the boosted voltage Vpump from the charge pump booster circuit 13.
The output transistor M8, being driven from the differential stage 5, thus sets the secondary program voltage Vpd either to the value of the boosted voltage Vpump supplied by the charge pump booster circuit 13 or a multiple value of the control voltage V.sub.BG independent of temperature generated by a so-called bandgap circuit 12, as by the following relation: EQU Vpd=(1+R1/R2)*V.sub.BG (2)
Similar as the differential regulator 4 of FIG. 2, the output transistor M8 has been shown separately for convenience of illustration, but would actually be a part of an operational amplifier also including the differential stage 5.
The non-inverting input terminal 8 of the differential stage 5 is connected to the column decoder 3 through a first resistive element R1 of the resistive divider R1/R2 and to the ground voltage reference GND through a second resistive element R2 of the divider.
However, the feedback differential regulator 11 with no adjustment feature has shortcomings, foremost among which is the fact that the equivalent series resistance RC of the column decoder 3 increases with temperature, thereby lowering the effective voltage applied to the drain terminal D1 of the cell to be programmed, for the same current I.sub.C taken up.
Illustratively, with a program current of 400 .mu.A per cell, the voltage drop .DELTA.V.sub.C across the decoder 3 is approximately 200 mV at a temperature of-40.degree. C., and reaches 350 mV at a temperature of 120.degree. C.
Thus, it can be seen that the program voltage Vd regulation provided for the drain terminal D1 by the feedback differential regulator 11 without adjustment feature shown in FIG. 3 becomes quite inefficient as temperature increases, the voltage applied to the terminal D1 not being sufficiently high.